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+<br>Personally I don’t think we are going to see the road between memory and storage be all that muddled sooner or later. Sure, 3D XPoint is much more responsive than Flash. But Flash isn’t all that spectacular as is. The everyday exhausting drive has entry latencies around 4ms on common. Flash can attain properly bellow µs latency, however for very small arrays. That is costly and mostly seen in Microcontrollers that execute directly from their Flash. "Enterprise grade" flash that optimizes at value/GB can have far higher latency, in the few to tens of µs area. 3D Xpoint is a bit of a wash. I have seen quoted figures of sub 350ns write latency, but that is probably going for a single cell, not an array. Optane modules from Intel however have typical latencies around 5-15µs, but this is from a "system" perspective, ie, protocol and controller overhead comes into play, as well as one’s software program setting.<br>
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+<br>DRAM then again has access latencies round 2-15ns at current. The problem with latency is that it leads to our processor stalling resulting from not getting the data in time. One can prefetch, but branches makes prefetching more durable, since what side do you have to fetch? Branch prediction partly solves this problem. However from a performance standpoint,  [neural entrainment audio](https://trade-britanica.trade/wiki/User:AlfonsoBrinker) we should always fetch each sides. But when we've extra latency, we need to prefetch even earlier, risking more branches. In other words, peak bandwidth required by our processor will increase at an exponential charge compared to latency. A charge that is software dependent as well. Caching might seem just like the trivial solution to the difficulty, however the effectivity of cache is proportional to the latency. To a degree, cache is a magic bullet that just makes memory latency disappear. However each time an software calls for one thing that isn’t in cache, then the application stalls, so long as there's threads to take its place that even have data to work on, then you won’t have a performance deficit other than thread switching penelties, however should you don’t have such threads, then the CPU stalls.<br>
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+<br>One can ensure that more threads have their data by simply making the cache greater, but cache is quite a bit costlier than DRAM. In the end, it all leads to the fact that growing latency will require an arbitrary quantity extra cache for an analogous system performance. Going from the few ns latency of DRAM to the couple of µs latency of present persistent memory will not be sensible as an precise alternative for DRAM, even when it reduces its latency to a one hundredth it is still not impressive so far as memory goes. Although, the usage of persistent DIMMs for storage caching or as a "RAM drive" of kinds still has main advantages, however for program execution it's laughable. And i don’t suspect this to alter any time soon. However I can see a future where the main memory [relocates](https://www.medcheck-up.com/?s=relocates) into the CPU. Where the CPU itself has an HBM memory chip or 4 on it supplying relatively low latency and high bandwidth memory to the CPU, whereas the exterior buses are used for IO and storage. However this isn’t all that life like in more skilled applications, since some workstation functions actually wants 10’s-100’s of GB of actual RAM to get good performance.<br>
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